There are many environments in which isochronous (synchronous) displays exist. For example LCD and CRT displays may be isochronous. Isochronous displays require data to be displayed in a synchronous manner, with a refresh process. Isochronous displays cannot tolerate delays in the arrival of data. These situations are known as data under-run conditions. Data under-run conditions may cause displays to become corrupt with visibly bad pixels and sometimes even bad rows or fields. Accordingly, there is a requirement to provide a display controller which overcomes this problem. This is particularly the case with resource limited and cost limited handheld devices, but the problem exists with any isochronous display.
There are a number of solutions that have been proposed to this problem. One such proposal is disclosed in the US 2003/0142058 (Inventor: Maghielse) and makes use of a first in first out (FIFO) type latency buffer. When the FIFO under-runs the display controller either stops or throttles the display pixel clocks; or repeats the last pixel data keeping the clock running. FIG. 1 shows an example of a display controller which includes a direct memory access (DMA) engine 100. This passes data to an input FIFO 102. The output from the input FIFO is passed through a palette random access memory (RAM) 106 and a dithering engine 108 to a formatter 110. The output data is then passed to the pins via an output FIFO 112.
This has a number of disadvantages, one disadvantage being that not all displays will tolerate the stalling of the pixel clock. In addition, long repetition time of the last pixel can be visible in most cases and thereby does not solve the problem of “bad pixels”.
In order to minimise costs of hand held and mobile devices a number of proposals have been made which adopt a system architecture and unified memory and avoid using separate memory for display refresh buffers. Because of this the display refresh process depends not only on the display controller access to memory but also on other device activities such as the CPU, the DMA and so on. The access by other devices may cause fluctuating memory latency. It is this fluctuating memory latency that can also cause the data under-run in a display controller FIFO.
One object of the present invention is to provide an efficient method of feeding data to a display. Another object of the present invention is to reduce visible display corruption. A still further object to the present invention is to provide a display controller architecture which overcomes at least some of the disadvantages of the prior art.